1. Field
A number of low k materials which meet the microelectronics industry dielectric constant requirements contain carbon and are deposited by plasma enhanced chemical vapor deposition (PECVD). The carbon containing low k dielectrics need to have a uniform carbon distribution. In addition, the presence of carbon affects the adhesion between a low k dielectric layer and an underlying or overlying diffusion barrier layer.
2. Description of the Background Art
This section describes background subject matter related to the disclosed embodiments of the present invention. There is no intention, either express or implied, that the background art discussed in this section legally constitutes prior art.
The next generation of semiconductor devices will be the 32 nm “technology node”. This small feature size requires that each layer of material which forms a part of the device structure be able to perform its function in a smaller space than was previously available. As a result, during the deposition of very thin layers (350 Å or less) of material which make up the device, abrupt changes in material compositions and structures may occur which have undesirable effects, (causing problems in the device function). For example, a layer of low k material is applied for purposes of providing an electrically insulating function, but just enough to control electrical signal transfer while not slowing the functioning of the device as a whole. A number of low k materials have been developed in recent years, and frequently these materials are used in contact with a surface of a diffusion barrier layer which prevents migration of conductive materials into adjacent semiconductor or dielectric layers.
It is important that there be good adhesion between the low k dielectric layer and the diffusion barrier layer. This is important for device performance integrity. It is also important during fabrication of the devices, because the most commonly used processes for creating “multi-layer metal” devices (i.e. multi-layered connectivity devices which are useful in reducing device size) are damascene processes which make use of flattening, milling processes such as chemical mechanical polishing. These milling processes create stress at interfaces between layers present in the device structure at the time of milling.
The stresses created between device layers during a process such as chemical mechanical polishing (CMP) can deform the device, separate interfacial surfaces, and cause performance defects.
Low k dielectric materials which have been developed in recent years and the manner in which these materials are used are described in the related patents and applications previously referred to herein, as well as others mentioned below, for example. This is not an all inclusive list of the background art, but hopefully provides a general understanding of the technology which is improved upon by the present invention.
U.S. Pat. No. 6,455,417 to Bao et al., issued Sep. 24, 2002, titled: “Method for Forming Damascene Structure Employing Bi-layer Carbon doped Silicon Nitride/Carbon Doped Silicon Oxide Etch Stop Layer”, describes a damascene method for forming a microelectronic structure, which employs a first etch stop/liner layer formed on a substrate, where the first etch stop/liner layer comprises a carbon doped silicon nitride material and a second layer formed upon the first layer, where the second layer is a carbon doped silicon oxide dielectric material. (Abstract) In a preferred embodiment of the Bao et al. structure, both the carbon doped silicon nitride material and the carbon doped silicon oxide material are formed by employing a PECVD method. Typically the starting precursors used in the PECVD process include an organosilane as a silicon and carbon source material. The organosilane material may be reacted with nitrogen source material such as nitrogen, ammonia, or hydrazine, for example to form the carbon doped silicon nitride. The organosilane material may be reacted with an oxygen source material such as oxygen, ozone, nitrous oxide, nitric oxide, carbon monoxide, and carbon dioxide to form a carbon doped silicon oxide.
Schmitt et al. U.S. Pat. No. 7,611,996 B2 describes the deposition of low k dielectric layers using chemical vapor deposition (CVD), and preferably plasma enhanced CVD (PECVD), so that reactant gases used to produce depositing films can be excited by the plasma and a lower temperature is required for film deposition. A discussion of various CVD deposited films and their function includes the consideration that as devices get smaller, the contribution of resistivity from structures of multiple layered films increases, slowing down the performance of a device. In addition, smaller device geometries result in an increase in parasitic capacitance between devices. Parasitic capacitance between metal interconnects on the same or adjacent layers in a circuit can result in crosstalk between the metal lines or interconnects and/or resistance-capacitance (RC) delay, thereby reducing the response time of the device and degrading the overall performance of the device. The problem becomes worse as the number of levels of metal interconnects is increased.
To reduce the parasitic capacitance between metal interconnects on the same or adjacent layers, it has been necessary to change the low k dielectric material used between the metal lines or interconnects to a material having an increasingly lower dielectric constant. A dielectric constant below 2.5 is mentioned as desirable in the Schmitt et al. patent. The material developed to obtain this dielectric constant was a nano-porous silicon oxide film having dispersed microscopic gas voids. This low k dielectric material is said to be typically deposited over the surface of a barrier layer which is comprised of a PECVD silicon oxide, silicon nitride, silicon oxynitride, or hydrogenated silicon carbide.
The Lee et al. patent (U.S. Pat. No. 7,151,053 B2) describes a method of depositing a barrier layer on a substrate by reacting a gas comprising an oxygen-containing organosilicon compound, a compound comprising oxygen and carbon, and an oxygen-free organosilicon compound, where the resulting film deposited is an oxygen-doped silicon carbide layer having an oxygen content of about 15 atomic % or less. In another embodiment, the reactants include a compound comprising oxygen and carbon and an oxygen-free organosilicon compound, which can also be used to produce an oxygen-doped silicon carbide layer having an oxygen content of about 15 atomic % or less.
The development of silicon oxycarbide films having both a low dielectric constant and desirable chemical and mechanical properties has turned out to be challenging. It has been observed that silicon oxycarbide films which have a desirably low dielectric constant of less than 2.5 often do not adhere well to an underlying barrier layer, such as a silicon and carbon-containing barrier layer. Embodiments of the invention described in the Lakshmanan et al. patent (U.S. Pat. No. 7,189,658 B2) describe a method of depositing a low k dielectric layer, where the low k dielectric layer is deposited in a manner such that there is an oxygen concentration gradient within the deposited layer. The underlying barrier layer may be a silicon carbide, nitrogen-doped silicon carbide, oxygen-doped silicon carbide, or oxygen and nitrogen-doped silicon carbide layer. The low k dielectric layer deposited over the barrier layer is formed using a PECVD process in which the processing gas feed comprises an organosilicon compound and an oxidizing gas, where the flow rate of the organosilicon compound is increased as the deposition progresses. This provides a higher oxygen content and a lower carbon content at the interface between the barrier layer and the low k dielectric layer.
The concept of producing a series of layers to create microelectronic structure having desired properties within a PECVD processing chamber is also described in the Edelstein et al. patent (U.S. Pat. No. 7,615,482). A method is disclosed in which a starting substrate surface is a layer of dielectric or conductive material. A layer of oxide (silicon oxide) is formed on the substrate surface, where the oxide layer contains essentially no carbon. A graded transition layer is then formed over the oxide layer, where the graded transition layer has essentially no carbon at the interface with the oxide layer and gradually increases in carbon content towards a porous SiCOH layer, which forms the upper portion of the low dielectric constant layer. The precursor material used to produce the SiCOH layer is said to be ramped up while the oxygen concentration in the PECVD feed gas is ramped down.
As discussed with reference to FIGS. 2 and 3 of the Edelstein et al. patent, there are likely problems with adhesion between the various layers which have different chemical compositions. For purposes of illustration, please see FIG. 1 of the present application, which illustrates a renumbered Edelstein et al. example for a two metallization layer structure. One of skill in the art will recognize that there may be up to 7 or more metallization layers, depending on the device structure. In FIG. 1A, the semiconductor structure 100 includes a semiconductor material 102 which underlies a low k dielectric layer 104 which contains a metal line 106. Overlying metal line 106 is a capping layer 110, which may be a silicon carbide material such as SiCH or SiCHN, as described in the Edelstein et al. patent. Overlying capping layer 110 is an interfacial structure 112, which is said to be made up of two layers 112a and 112b, as illustrated in more detail in FIG. 1B.
Layer 112a is said to be an oxide layer having essentially no carbon, where “essentially” is defined as ranging from 0.1 to 3 atomic percent carbon. A carbon content of this amount is said not to adversely affect the performance of the oxide layer 112a. Layer 112b is said to be a transition layer, which transitions from an oxide layer having essentially no carbon to a porous SiCOH layer. Overlying the surface of layer 112b is a homogeneous low k dielectric layer of SiCOH which is shown as layer 114. The low k dielectric layer 114 is equivalent to the low k dielectric layer 104. A connective contact via 108 containing a conductive fill material 108 is surrounded by low k dielectric layer 104. A second level metal line 116 is in contact with the conductive material present in connective via 108.
Overlying second metal line 116 is a second capping layer 120, which may be a silicon carbide material such as SiCH or SiCHN, as described in the Edelstein et al. patent. Overlying second capping layer 120 is a second interfacial structure 122, which is made up of two layers (not shown) which would be the equivalent of layers 112a and 112b which are shown in FIG. 1B. A second level contact via 118 filled with conductive material makes the connection with the second metal line 116, and may connect to additional layers of metallization which are not shown above second level via 118. A third homogeneous low k dielectric layer 124 of SiCOH surrounds contact via 118.
As discussed in the Edelstein et al. patent, the problem with the structure shown in prior art FIGS. 1A and 1B (of the present application) is said to be that adhesion tends to be inadequate between the SiCOH layer (104, 114, and 124) and the underlying layer, which may be a semiconductor material 102 (such as silicon, for example) or may be a capping (barrier) material layer (112 and 122) which has typically been a silicon carbide-based material. The transition layer, shown as 112b in prior art FIG. 1B (shown in the present application) is intended to improve the adhesion between layer 112b and underling layer 112a, which is the silicon oxide layer which contains essentially no carbon. Further, layer 112a is said to have been demonstrated to bond well to the surface of the low k dielectric SiCOH layer (104, 114 and 124).
In the Edelstein et al. patent, the key to deposition of the transition layer (shown as 112b in the present application prior art FIG. 1B) is said to be that there is a smooth transition in the amount of carbon present in the depositing film as the amount of carbon is increased. However, finding a method of achieving this smooth transition has been somewhat elusive. For example, the Edelstein et al., patent teaches that the feed of reactive precursors shown in FIG. 5 of the Edelstein et al. patent results in a large carbon peak in the carbon graded transition layer formed, eventually resulting in a mechanically weak interfacial layer with the underlying surface. To solve this problem, a different introduction schedule of the reactants into the chamber, of the kind shown in Edelstein et al. FIG. 6 was used. This was said to still result in a carbon peak and an oxygen dip during film deposition, both of which lead to a mechanically weak interfacial layer at the underlying surface. Finally, a revised introduction schedule of reactants into the chamber, of the kind shown in Edelstein et al. FIG. 7 (prior art FIG. 2 of the present application) is said to provide a transition layer in which both carbon and porosity gradually and uniformly increase.
As mentioned above, prior art FIG. 2 of the present application shows the Edelstein et al FIG. 7. FIG. 200 is a graph showing relative flow rates for various precursor materials on axis 204 and a time period related to the PECVD film deposition process at which the flow is taking place on axis 202. The actual flow rates are not specified in the Edelstein disclosure. The time periods are specified, where T1 is said to range from 1-4 seconds, T2 is said to range from 2-4 seconds, T3 is said to be greater than T2. T4 is described as the time when all flows are stabilized at values to deposit the porous SiCOH low k dielectric film. T4 is said to typically range from 10 seconds to 200 seconds. Curve 206 represents a porogen (one of the kinds known in the art) precursor flow, the precise composition of which is not defined in the Edelstein et al. patent. Curve 208 represents oxygen flow, and Curve 210 represents the SiCOH low k dielectric precursor flow. The low k dielectric precursor materials are not specifically described. T2 is said to be the time at which the dielectric precursor flow is stable. The porogen precursor is said to be introduced during the T1-T2 interval. T3 is said to be the time at which the porogen precursor flow is stable. The ramp up rate of the porogen precursor may be lower than the ramp up rate of the dielectric precursor, as is shown in the present prior art FIG. 2. The interval between T2 and T3 is said to be preferably as short as possible.
Despite all of this effort, the adhesion between barrier layers and low k dielectric layers has continued to cause problems with respect to the structural stability of the overall multi metal layer structures which include low k dielectric layers. The present invention provides an improvement over the prior art described above, by providing an improved device structure which inherently solves many of the prior art problems. While the present invention makes use of many of the same precursor materials as those described in the art, the manner in which the materials are applied is different, and this provides the improved device structure.